Integrated circuits (ICs) are used in various applications and devices. Programmable circuits, which may be found in field-programmable gate array (FPGA) devices, may include logic blocks, generic structures, and input-output structures that can be configured to perform a variety of functions and support a variety of different protocols. These circuits may include embedded memory blocks that are operable to cater for different design requirements. Programmable circuits as well as other types of ICs generally include input-output (I/O) circuits that can be used to support multiple I/O protocols, including different memory interfaces.
Generally, the speed of the device varies depending on which memory interfaces are used and the particular design implemented. For instance, the data rate of a double data rate type three (DDR3) interface may go up to 3.2 Gbps. Memory blocks in a programmable circuit are generally embedded in a core region of the programmable circuit and signals to and from the embedded memory blocks travel through I/O circuitry that are generally placed on the perimeter of the programmable circuit. The core region of the programmable circuit and the I/O circuitry typically operate in different power domains.
For instance, the core region of the programmable circuit may operate at 0.85v while the I/O circuitry around the core region may operate at a higher voltage for different interfaces, e.g., 1.5v for the DDR3 interface. As such, a level shifter circuit, i.e., a circuit that connects one circuit that uses one logic level or power level to another circuit that uses another logic level or power level, is usually placed between the I/O circuits and the embedded memory blocks in the core region of the programmable circuit.
However, conventional level shifter circuits, which are typically latch-type circuits, need to overcome their previous state when switching from one state to another state. Therefore, compared to other logic elements, such as inverters, gates, etc., level shifter circuits usually operate at a lower speed and create bottlenecks that slow down memory interfaces.